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<div class="header">
  <div class="headertitle"><div class="title">GPIO_TypeDef Struct Reference<div class="ingroups"><a class="el" href="group___c_m_s_i_s___device.html">CMSIS_Device</a> &raquo; <a class="el" href="group__stm32h723xx.html">Stm32h723xx</a> &raquo; <a class="el" href="group___peripheral__registers__structures.html">Peripheral_registers_structures</a></div></div></div>
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<p>General Purpose I/O.  
 <a href="#details">More...</a></p>

<p><code>#include &lt;<a class="el" href="stm32h723xx_8h_source.html">stm32h723xx.h</a>&gt;</code></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 id="header-pub-attribs" class="groupheader"><a id="pub-attribs" name="pub-attribs"></a>
Public Attributes</h2></td></tr>
<tr class="memitem:ac2505d096b6b650f1647b8e0ff8b196b" id="r_ac2505d096b6b650f1647b8e0ff8b196b"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ac2505d096b6b650f1647b8e0ff8b196b">MODER</a></td></tr>
<tr class="memitem:a910885e4d881c3a459dd11640237107f" id="r_a910885e4d881c3a459dd11640237107f"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a910885e4d881c3a459dd11640237107f">OTYPER</a></td></tr>
<tr class="memitem:a0d233d720f18ae2050f9131fa6faf7c6" id="r_a0d233d720f18ae2050f9131fa6faf7c6"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a0d233d720f18ae2050f9131fa6faf7c6">OSPEEDR</a></td></tr>
<tr class="memitem:a44ada3bfbe891e2efc1e06bda4c8014e" id="r_a44ada3bfbe891e2efc1e06bda4c8014e"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a44ada3bfbe891e2efc1e06bda4c8014e">PUPDR</a></td></tr>
<tr class="memitem:acf11156409414ad8841bb0b62959ee96" id="r_acf11156409414ad8841bb0b62959ee96"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#acf11156409414ad8841bb0b62959ee96">IDR</a></td></tr>
<tr class="memitem:a6fb78f4a978a36032cdeac93ac3c9c8b" id="r_a6fb78f4a978a36032cdeac93ac3c9c8b"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a6fb78f4a978a36032cdeac93ac3c9c8b">ODR</a></td></tr>
<tr class="memitem:acd6f21e08912b484c030ca8b18e11cd6" id="r_acd6f21e08912b484c030ca8b18e11cd6"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#acd6f21e08912b484c030ca8b18e11cd6">BSRR</a></td></tr>
<tr class="memitem:a95a59d4b1d52be521f3246028be32f3e" id="r_a95a59d4b1d52be521f3246028be32f3e"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a95a59d4b1d52be521f3246028be32f3e">LCKR</a></td></tr>
<tr class="memitem:a2245603433e102f0fd8a85f7de020755" id="r_a2245603433e102f0fd8a85f7de020755"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a2245603433e102f0fd8a85f7de020755">AFR</a> [2]</td></tr>
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<a name="details" id="details"></a><h2 id="header-details" class="groupheader">Detailed Description</h2>
<div class="textblock"><p>General Purpose I/O. </p>
</div><a name="doc-variable-members" id="doc-variable-members"></a><h2 id="header-doc-variable-members" class="groupheader">Member Data Documentation</h2>
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<h2 class="memtitle"><span class="permalink"><a href="#a2245603433e102f0fd8a85f7de020755">&#9670;&#160;</a></span>AFR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t GPIO_TypeDef::AFR[2]</td>
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<p>GPIO alternate function registers, Address offset: 0x20-0x24 </p>

</div>
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<a id="acd6f21e08912b484c030ca8b18e11cd6" name="acd6f21e08912b484c030ca8b18e11cd6"></a>
<h2 class="memtitle"><span class="permalink"><a href="#acd6f21e08912b484c030ca8b18e11cd6">&#9670;&#160;</a></span>BSRR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t GPIO_TypeDef::BSRR</td>
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<p>GPIO port bit set/reset, Address offset: 0x18 </p>

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<a id="acf11156409414ad8841bb0b62959ee96" name="acf11156409414ad8841bb0b62959ee96"></a>
<h2 class="memtitle"><span class="permalink"><a href="#acf11156409414ad8841bb0b62959ee96">&#9670;&#160;</a></span>IDR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t GPIO_TypeDef::IDR</td>
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<p>GPIO port input data register, Address offset: 0x10 </p>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t GPIO_TypeDef::LCKR</td>
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<p>GPIO port configuration lock register, Address offset: 0x1C </p>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t GPIO_TypeDef::MODER</td>
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<p>GPIO port mode register, Address offset: 0x00 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a6fb78f4a978a36032cdeac93ac3c9c8b">&#9670;&#160;</a></span>ODR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t GPIO_TypeDef::ODR</td>
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<p>GPIO port output data register, Address offset: 0x14 </p>

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<p>GPIO port output speed register, Address offset: 0x08 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a910885e4d881c3a459dd11640237107f">&#9670;&#160;</a></span>OTYPER</h2>

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<p>GPIO port output type register, Address offset: 0x04 </p>

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<p>GPIO port pull-up/pull-down register, Address offset: 0x0C </p>

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<hr/>The documentation for this struct was generated from the following file:<ul>
<li>C:/Users/ASUS/Desktop/dm-ctrlH7-balance-9025test/Drivers/CMSIS/Device/ST/STM32H7xx/Include/<a class="el" href="stm32h723xx_8h_source.html">stm32h723xx.h</a></li>
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